CY8C9520A-24PVXIT单片机解密

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　　Architecture
　　The “Top Level Block Diagram” on page 1 illustrates the device block diagram. The main blocks include the control unit, PWMs,EEPROM, and I/O ports. The control unit executes commands 2
　　received from the IC bus and transfers data between other bus devices and the master device.
　　The on chip EEPROM can be separated conventionally into two regions. The first region is designed to store data and is available 2 for byte wide read/writes through the I C bus. It is possible to prevent write operations by setting the WD pin to high. All EEPROM operations can be blocked by configuration register settings. The second region allows the user to store the port and PWM default settings using special commands. These defaults are automatically reloaded and processed after device power on. The number of I/O lines and PWM sources are listed in the following table.